www.siliconstandard.com 1 of 7 n-channel enhancement-mode power mosfet bv dss 25v r ds(on) 12mw i d 11.8a the SSM7811GM acheives fast switching performance with low gate charge without a complex drive circuit. it is suitable for low voltage applications such as dc/dc pb-free; rohs-compliant so-8 product summary description notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. 3.mounted on a square inch of copper pad on fr4 board ; 125c/w when mounted on the minimum pad area required for soldering. converters and general load-switching circuits. the SSM7811GM is supplied in an rohs-compliant so-8 package, which is widely used for medium power commercial and industrial surface mount applications. s s s g d d d d so-8 absolute maximum ratings symbol parameter value units v ds v gs i d i dm p d w/c t stg t j symbol parameter value units r qja maximum thermal resistance, junction-ambient 3 50 c/w drain-source voltage 25 v gate-source voltage 12 v continuous drain current, t c = 25c 11.8 a t c = 70c 9.4 a pulsed drain current 1 30 a total power dissipation, t c = 25c 2.5 w -55 to 150 c operating junction temperature range -55 to 150 c linear derating factor 0.02 thermal characteristics storage temperature range ssm 7 811 g m 9 /16/2006 re v.3.01
www.siliconstandard.com 2 of 7 electrical characteristics (at tj = 25c, unless otherwise specified) notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 25 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.1 - v/c r ds(on) static drain-source on-resistance 2 v gs =4.5v, i d =11.8a - 10 12 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 0.5 - 1.2 v g fs forward transconductance v ds =15v, i d =11.8a - 30 - s i dss drain-source leakage current v ds =25v, v gs =0v - - 1 ua v ds =20v ,v gs =0v, tj = 70c - - 25 ua i gss gate-source leakage current v gs =12v - - 100 na q g total gate charge 2 i d =11.8a - 32 - nc q gs gate-source charge v ds =20v - 2.6 - nc q gd gate-drain ("miller") charge v gs =5v - 15.5 - nc t d(on) turn-on delay time 2 v ds =15v - 12 - ns t r rise time i d =1.5a - 28 - ns t d(off) turn-off delay time r g =3.3w , v gs =5v - 41 - ns t f fall time r d =10w - 40 - ns c iss input capacitance v gs =0v - 800 - pf c oss output capacitance v ds =25v - 460 - pf c rss reverse transfer capacitance f=1.0mhz - 215 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward voltage 2 i s =2.3a, v gs =0v - - 1.2 v i sd continuous source current ( body diode ) v d =v g =0v, v s =1.2v - - 2.08 a ssm 7 811 g m 9 /16/2006 re v.3.01
www.siliconstandard.com 3 of 7 ssm 7 811 g m 9 /16/2006 re v.3.01 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature 8 10 12 14 16 18 23456 v gs (v) r ds(on) (m w ) i d =11.8a t c =25 o c 0.60 0.80 1.00 1.20 1.40 1.60 1.80 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) v gs =4.5v i d =11.8a 0 10 20 30 40 0 0.5 1 1.5 2 2.5 3 v ds , drain-to-source voltage (v) i d , drain current (a) t c =25 o c 4.5v 3.5v 3.0v 2.5v v gs =2.0v 0 10 20 30 0 0.5 1 1.5 2 2.5 3 v ds , drain-to-source voltage (v) i d , drain current (a) t c =150 o c 4.5v 3.5v 3.0v 2.5v v gs =2.0v
www.siliconstandard.com 4 of 7 SSM7811GM 9/16/2006 rev.3.01 fig 5. maximum drain current vs. fig 6. typical power dissipation case temperature fig 7. maximum safe operating area fig 8. effective transient thermal impedance 0 0.5 1 1.5 2 2.5 3 0 30 60 90 120 150 t c , case temperature ( o c) p d (w) 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a r thja =125 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor = 0.5 single pulse 0.01 0.1 1 10 100 0.1 1 10 100 v ds (v) i d (a) t c =25 o c single pulse 1ms 10ms 100ms 1s 10s d c 0 3 6 9 12 15 25 50 75 100 125 150 t c , case temperature ( o c) i d , drain current (a)
www.siliconstandard.com 5 of 7 ssm 7 811 g m 9 /16/2006 re v.3.01 fig 9. gate charge characteristics fig 10. typical capacitance characteristics fig 11. forward characteristic of fig 12. gate threshold voltage vs. reverse diode junction temperature 100 1000 10000 1 5 9 13 17 21 25 29 v ds (v) c (pf) f =1.0mhz ciss coss crss 0 2 4 6 8 10 12 0 102030405060 q g , total gate charge (nc) v gs , gate to source voltage (v) v ds =10v v ds =15v v ds =20v 0.01 0.10 1.00 10.00 100.00 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 v sd (v) i s (a) t j =25 o c t j =150 o c 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -50 0 50 100 150 junction temperature ( o c ) v gs(th) (v) i d =11.8a
www.siliconstandard.com 6 of 7 SSM7811GM 9/16/2006 rev.3.01 fig 13. switching time circuit fig 14. switching time waveform fig 15. gate charge circuit fig 16. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 5v q gs q gd q g charge 0.6 x rated v ds to the oscilloscope - + 5 v d g s v ds v gs r g r d 0.8 x rated v ds to the oscilloscope - + d g s v ds v gs i d i g
www.siliconstandard.com 7 of 7 physical dimensions part marking packing: moisture sensitivity level msl3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (mbb). symbol min max a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27(typ) h 5.80 6.50 l 0.38 1.27 d h e a b a1 c e l dimensions do not include mold protrusions. part number: 7811gm = SSM7811GM 7811gm ywwsss date/lot code: (ywwsss) y = last digit of the year ww = week sss = lot code sequence all dimensions in millimeters. ssm 7 811 g m 9 /16/2006 re v.3.01 information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties.
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